1. Field of the Invention
Present invention relates to an opto-electronic integrated circuit (OEIC) having a semiconductor optical device and electronic device integrated monolithically on one substrate.
2. Related Background Art
Following methods are known as a method for producing the opto-electronic integrated circuit.
First method as described in Presentation No. S9-1, 1987 National Conference of Semiconductor Materials Section, Association of Electronic Information Communication, is composed of steps of; forming a photodiode (PD) as an optical device on an indium phosphide (InP) substrate by the vapor phase epitaxy (VPE), forming a gallium arsenide (GaAs) layer next to the PD on the InP substrate, and forming a field effect transistor (FET) thereon as an electronic device.
Second method, as described in Presentation No. S9-3, 1987 National Conference of Semiconductor Materials Section, Association of Electronic Information Communication, is composed steps of; forming a recess on an InP substrate, forming PD by the VPE in the recess, removing the layer for the PD in a FET region, forming an epitaxial layer for the FET, and forming the FET on the epitaxial layer;
And third method, as described in Presentation No. S9-2, 1987 National Conference of Semicondcutor Materials Section, Association of Electronic Information Communication is composed of steps of; forming a n-GaInAs layer for a junction type field effect transistor (J-FET) and an epitaxial layer for a PD respectively on an InP substrate, and performing beryllium (Be) ion implantation to form a p-region so as to form the PD and the J-FET.
But, in the first and the second methods, it is necessary to grow an epitaxial layer for a PD and remove the unnecessary potion thereof to grow anew an epitaxial layer for a FET. The production steps are accordingly complicated. This results in the problems that it is difficult to make highly pure crystals in growing anew the epitaxial layer, with a result that a FET having good characteristics cannot be reproduced with ease.
The third method requires a Be ion implantation step and an annealing step. This results in the problem that the method is accordingly complicated. Another problem is that wafers is bent in the annealing step, and the lithography in a following step result in low precision. Further another problem is that the method for the third circuit has to use as a FET a J-FET, whose high frequency characteristics are not good.